MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 455

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Chapter 12
U-Bus to IMB3 Bus Interface (UIMB)
The U-bus to IMB3 bus interface (UIMB) structure is used to connect the CPU internal unified bus (U-bus)
to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3. The
UIMB interface (see
decode, data multiplexing, intrasystem communication (interrupts), and clock generation to allow
communication between U-bus and the IMB3. The seven submodules are:
12.1
Freescale Semiconductor
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U-bus interface
IMB3 interface
Address decoder
Data multiplexer
Interrupt synchronizer
Clock control
Scan control
Provides complete interfacing between the U-bus and the IMB3:
— 15 bits (32 Kbytes) of address decode on IMB3
— 32-bit data bus
— Read/write access to IMB3 module registers
— Interrupt synchronizer
— Monitoring of accesses to unimplemented addresses within UIMB interface address range
— Burst-inhibited accesses to the modules on IMB3
Support of 32-bit and 16-bit bus interface units (BIUs) for IMB3 modules
Half and full speed operation of IMB3 bus with respect to U-bus
Simple “slave only” U-bus interface implementation
— Transparent mode operation not supported
— Relinquish and retry not supported
Supports scan control for modules on the IMB3 and on the U-bus
Features
Modules on the IMB3 bus can only be reset by SRESET. Some modules
may have a module reset, as well.
Figure
12-1) consists of seven submodules that control bus interface timing, address
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
12-1