MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 1371

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Note: All delays are in system clock periods.
Freescale Semiconductor
1
2
3
MDASM pin high time
Input capture resolution
Input pin to Counter Bus capture delay
Input pin to interrupt flag delay
Input pin to PIN delay
Counter bus resolution
Output pulse width
Compare resolution
Counter Bus to pin change
Counter Bus to interrupt flag set.
If the counter bus capture occurs when the counter bus is changing then the capture is delayed one cycle. In
situations where the counter bus is stable when the input capture occurs the t
cycles (the one-cycle uncertainty is due to the synchronizer).
Maximum resolution is obtained by setting CPSMPSL[3:0] =0x2 and MDASMSCR_CP[7:0] =0xFF.
Maximum output resolution and pulse width depends on counter (e.g., MMCSM) and MCPSM prescaler
settings.
MDAI input pin
f
SYS
Characteristics
f
SYS
is the internal system clock for the IMB3 bus.
3
3
Figure G-56. MDASM Minimum Input Pin Timing Diagram
Table G-26. MDASM Timing Characteristics (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Output Modes: (OC, OPWM)
t
PPER
min
Symbol
t
NOTE
t
t
t
t
t
CBFLG
COMR
t
PULW
CAPR
PCAP
t
PFLG
t
t
CBR
CBP
PHI
PIN
t
min
PLO
Min
—
—
—
2
1
2
1
2
PCAP
t
min
PHI
has a maximum delay of two
3
3
66-MHz Electrical Characteristics
Max
—
3
2
—
2
2
3
2
1
2
2
G-65