MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 989

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

24.7.1
The READI signal interface provides the function of transmitting messages from the message queues to
the external tools. The signal interface also provides the control for timing and logic for formatting the
messages.
24.7.1.1
The READI module implements one MCKO, MCKI, EVTI, RSTI, MSEO, and MSEI signal. It also
implements one or two MDI and two or eight MDO signals. The input signals are synchronized to the
MCKI input clock and the output signals are synchronized to the free running MCKO output clock. The
MCKI input clock should be synchronised to the MCKO ouput clock to ensure correct message reception.
The READI signal definition is outlined in
Freescale Semiconductor
5001 Signal
MDO[7:0] or
IEEE-ISTO
MDO[1:0]
MDI[1:0]
MCKO
MSEO
Name
MCKI
MDI0
MSEI
RSTI
EVTI
or
Functional Description
Signals Implemented
MCKI clock frequency has to be less than or equal to one half of MCKO
clock frequency.
Output
Output
Output
Output
Input/
Input
Input
Input
Input
Input
Message Clock-Out (MCKO) is a free-running output clock to development tools for timing of
MDO and MSEO signal functions. MCKO is the same as the MCU system clock.
Message Data Out (MDO[7:0] or MDO[1:0]) are output signals used for uploading OTM, BTM,
DTM, and Read/Write Accesses. External latching of MDO will occur on rising edge of MCKO.
Eight signals are implemented. MDO[7:0] are used in full port mode, MDO[1:0] are used in
reduced port mode.
Message Start/End Out (MSEO) is an output signal which indicates when a message on the
MDO signals has started, when a variable length packet has ended, and when the message
has ended. 1 MSEO signal is implemented. External latching of MSEO will occur on rising
edge of MCKO.
Message Clock-In (MCKI) is a input clock from development tools for timing of MDI and MSEI
signal functions. MCKI frequency has to be less than or equal to one half of MCKO frequency.
Message Data In (MDI[1:0] or MDI[0]) are input signals used for downloading configuration
information, writes to user resources, etc. Internal latching of MDI will occur on rising edge of
MCKI. Two signals are implemented on the MPC561/MPC563. MDI[1:0] are used in full port
mode, MDI[0] only is used in reduced port mode.
Message Start/End In (MSEI) is an input signal which indicates when a message on the MDI
signals has started, when a variable length packet has ended, and when the message has
ended. 1 MSEI signal is implemented. Internal latching of MSEI will occur on rising edge of
MCKI.
Event In (EVTI) — The EVTI signal is level sensitive when configured for breakpoint
generation, otherwise it is edge sensitive.
Reset In (RSTI).
Table 24-17. Description of READI Signals
MPC561/MPC563 Reference Manual, Rev. 1.2
Table
NOTE
24-17.
Description of Signal
READI Module
24-21