MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 991

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

24.7.4
The protocol for the MCU receiving and transmitting messages via the auxiliary signals will be
accomplished with the MSEI and MSEO signal functions respectively. The MSEI signal will provide the
protocol for the MCU receiving messages, and the MSEO signal will provide the protocol for the MCU
transmitting messages.
The MSEI/MSEO protocol is illustrated in
MSEI/MSEO are used to signal the end of variable-length packets and messages. They are not required to
indicate end of fixed length packets. MSEI/MSEO are sampled on the rising edge of MCKI and MCKO
respectively.
Fixed width fields can be concatenated before variable length fields without regard to the individual fields
starting or ending at message N bit boundaries. Variable width fields must end at message N bit boundaries
(where N is MDI/MDO signals).
Figure 24-12
and MSEO are sampled on the rising edge of MCKO.
Freescale Semiconductor
6. Queued messages (program trace, data trace, and ownership trace)
MCKO
MSEO
MDO[7:0]
TCODE = 4
Number of Sequential Instructions since last taken branch = 4
Relative Address = 0x534
Signal Protocol
shows the basic relation between the MDO and MSEO signals, and packet structure. MDO
End of variable length packet
End of packet and message
Figure 24-12. Auxiliary Signal Packet Structure for Program Trace Indirect
Operation
Active
Start
Idle
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 24-18. MSEI/MSEO Protocol
00000100
“1”s at all clocks
Two “1”s followed by one “0”
“0”s at all clocks during transmission of a message
“0” followed by “1”
“0” followed by two or more “1”s
Table
Branch Message
00000001
24-18.
MSEO/MSEI State
00110100
00000101
Don’t care data
(idle clock)
00000000
READI Module
24-23