MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 26

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

19.2.2
19.2.3
19.2.4
19.2.5
19.2.6
19.3
19.3.1
19.3.2
19.3.3
19.3.4
19.3.5
19.3.6
19.3.7
19.3.8
19.3.9
19.4
19.4.1
19.4.2
19.4.3
19.4.4
19.4.5
19.4.6
19.4.7
19.4.8
19.4.9
19.4.10
19.4.11
19.4.12
19.4.13
19.4.14
19.4.15
19.5
20.1
20.2
20.3
20.3.1
20.3.2
Freescale Semiconductor
Paragraph
Number
TPU Operation .............................................................................................................. 19-3
Programming Model ..................................................................................................... 19-8
Time Functions ........................................................................................................... 19-23
Features ......................................................................................................................... 20-1
DPTRAM Configuration Block Diagram ..................................................................... 20-2
Programming Model ..................................................................................................... 20-2
Timer Channels ......................................................................................................... 19-2
Scheduler .................................................................................................................. 19-2
Microengine .............................................................................................................. 19-3
Host Interface ............................................................................................................ 19-3
Parameter RAM ........................................................................................................ 19-3
Event Timing ............................................................................................................ 19-3
Channel Orthogonality .............................................................................................. 19-4
Interchannel Communication .................................................................................... 19-4
Programmable Channel Service Priority .................................................................. 19-4
Coherency ................................................................................................................. 19-4
Emulation Support .................................................................................................... 19-4
TPU3 Interrupts ........................................................................................................ 19-5
Prescaler Control for TCR1 ...................................................................................... 19-5
Prescaler Control for TCR2 ...................................................................................... 19-7
TPU Module Configuration Register (TPUMCR) ................................................. 19-11
Development Support Control Register (DSCR) .................................................... 19-12
Development Support Status Register (DSSR) ...................................................... 19-13
TPU3 Interrupt Configuration Register (TICR) ..................................................... 19-14
Channel Interrupt Enable Register (CIER) ............................................................. 19-15
Channel Function Select Registers (CFSRn) .......................................................... 19-15
Host Sequence Registers (HSQRn) ........................................................................ 19-16
Host Service Request Registers (HSRRn) ............................................................. 19-17
Channel Priority Registers (CPRx) ......................................................................... 19-18
Channel Interrupt Status Register (CISR) .............................................................. 19-19
TPU3 Module Configuration Register 2 (TPUMCR2) ........................................... 19-19
TPU Module Configuration Register 3 (TPUMCR3) ............................................. 19-21
SIU Test Register (SIUTST) ................................................................................... 19-22
Factory Test Registers ............................................................................................ 19-22
TPU3 Parameter RAM ............................................................................................ 19-23
DPTRAM Module Configuration Register (DPTMCR) ......................................... 20-3
DPTRAM Test Register (DPTTCR) ......................................................................... 20-4
Dual-Port TPU3 RAM (DPTRAM)
MPC561/MPC563 Reference Manual, Rev. 1.2
Contents
Chapter 20
Title
Number
Page
xxvi