MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 273

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

6.2.2.2.3
6.2.2.2.4
SIMASK is a 32-bit read/write register. Each bit in the register corresponds to an interrupt request bit in
the SIPEND register.
SIMASK2 is a 32-bit read/write register. Each bit in the register corresponds to an interrupt request bit in
the SIPEND2 register.
SIMASK3 is a 32-bit read/write register. Each bit in the register corresponds to an interrupt request bit in
the SIPEND3 register.
When the bit is set, it enables the generation of an interrupt request to the RCPU. SIMASK, SIMASK2,
SIMASK3 are updated by software and cleared upon reset. It is the responsibility of the software to
determine which of the interrupt sources are enabled at a given time.
Freescale Semiconductor
SRESET
SRESET
Field
Field
Addr
IRQ20
MSB
IMB
16
0
SIU Interrupt Pending Register 3 (SIPEND3)
SIU Interrupt Mask Register (SIMASK)
Disable external interrupts in the core prior to changing any interrupt
controller related register (SIMASK, SIPEND, SIEL, or SISR). Refer to
MSR[EE] bit description in
handling of the EIC in
Operation.”
IRQ21
IMB
17
1
IRQ22
IMB
18
2
Figure 6-17. SIU Interrupt Pending Register 3 (SIPEND3)
IRQ23
IMB
19
3
MPC561/MPC563 Reference Manual, Rev. 1.2
IRQ
20
6
4
Section 6.1.4.4, “Enhanced Interrupt Controller
LVL
21
6
5
Table 3-11
IRQ24
IMB
22
6
0000_0000_0000_0000
0000_0000_0000_0000
NOTE
IRQ25
IMB
0x2F C044
23
7
and the note regarding special
—
IRQ26
IMB
24
8
IRQ27
IMB
25
9
IRQ
10
26
7
LVL
11
27
System Configuration and Protection
7
IRQ28
IMB
12
28
IRQ29
IMB
13
29
IRQ30
IMB
14
30
IRQ31
IMB
LSB
15
31
6-33