MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 438

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

L-Bus to U-Bus Interface (L2U)
11.3
Figure 11-1
MPC561/MPC563 bus architecture.
11-2
•
•
•
•
•
Supports a default global entry for memory space not covered by other regions:
— Default access protection
— Default guarded attribute
Interrupt generated upon:
— Access violation
— Load from guarded region
— Write to read-only region
The MSR[DR] bit (data relocate) controls DMPU protection on/off operation
Programming is done using the mtspr/mfspr instructions to/from implementation-specific special
purpose registers.
No protection for accesses to the CALRAM module on the L-bus (CALRAM has its own
protection options)
L2U Block Diagram
– Access protection: user or supervisor
– Guarded attribute: speculative or non-speculative
– Enable/disable option
– Read only option
shows a block diagram of the L-bus to U-bus interface as implemented in the overall
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor