DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 105

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Memory Blocks in Stratix V Devices
Memory Modes
Table 2–7. M20K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 2 of 2)
Figure 2–10. Simple Dual-Port Timing Waveforms
May 2011 Altera Corporation
4K x 4
4K x 5
2K x 8
2K x 10
1K x 16
1K x 20
512 x 32
512 x 40
Read Port
wraddress
q (asynch)
rdaddress
wrclock
rdclock
wren
data
rden
16K x 1
v
—
v
—
v
—
v
—
doutn-1
din-1
an-1
In simple dual-port mode, M20K blocks support separate write-enable and
read-enable signals. You can save power by keeping the read-enable signal low
(inactive) when not reading. Read-during-write operations to the same address can
either output a “don’t care” value or “old data” value. To choose the desired behavior,
set the read-during-write behavior to either don't care or old data in the RAM
MegaWizard™ Plug-In Manager. For more information, refer to
Behavior” on page
MLABs only support a write-enable signal. Read-during-write behavior for the
MLABs can be a “new data”, “don’t care” or “old data” value. The available choices
depend on the configuration of the MLAB.
Figure 2–10
dual-port mode with unregistered outputs. Registering the RAM outputs delay the q
output by one clock cycle.
bn
8K x 2
v
v
v
v
—
—
—
—
an
din
shows timing waveforms for read and write operations in simple
4K x 4
doutn
v
v
v
v
—
—
—
—
b0
a0
2–17.
4K x 5
—
v
—
v
—
v
—
v
a1
2K x 8
v
v
v
v
—
—
—
—
dout0
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Write Port
a2
b1
2K x 10
v
v
v
v
—
—
—
—
a3
1K x 16
v
—
v
—
v
—
v
—
din4
b2
a4
1K x 20
v
v
v
v
—
—
—
—
din5
“Read-During-Write
a5
b3
512 x 32
a6
din6
v
v
v
v
—
—
—
—
512 x 40
2–11
—
v
—
v
—
v
—
v