DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 165

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Clock Networks and PLLs in Stratix V Devices
Stratix V PLLs
May 2011 Altera Corporation
PLL Control Signals
1
1
Stratix V PLLs can also drive out to any regular I/O pin through the GCLK or RCLK
network. You can also use the external clock output pins as user I/O pins if you do
not require external PLL clocking.
You can use the pfdena, areset, and locked signals to control and observe PLL
operation and resynchronization.
pfdena
Use the pfdena signal to maintain the most recent locked frequency so your system
has time to store its current settings before shutting down. The pfdena signal controls
the PFD output with a programmable gate. If you disable PFD, the VCO operates at
its most recent set value of control voltage and frequency, with some long-term drift to
a lower frequency. The PLL continues running even if it goes out-of-lock or the input
clock is disabled. You can use either your own control signal or the control signals
available from the clock switchover circuit (activeclock, clkbad[0], or clkbad[1]) to
control pfdena.
areset
The areset signal is the reset or resynchronization input for each PLL. The device
input pins or internal logic can drive these input signals. When areset is driven high,
the PLL counters reset, clearing the PLL output and placing the PLL out-of-lock. The
VCO is then set back to its nominal setting. When areset is driven low again, the PLL
resynchronizes to its input as it re-locks.
You must assert the areset signal every time the PLL loses lock to guarantee the
correct phase relationship between the PLL input and output clocks. You can set up
the PLL to automatically reset (self reset) after a loss-of-lock condition using the
Quartus II MegaWizard Plug-In Manager. You must include the areset signal if
either of the following conditions is true:
■
■
If the input clock to the PLL is not toggling or is unstable after power up, assert the
areset signal after the input clock is stable and within specifications.
locked
The locked signal output of the PLL indicates that the PLL has locked onto the
reference clock and the PLL clock outputs are operating at the desired phase and
frequency set in the MegaWizard Plug-In Manager. The lock detection circuit provides
a signal to the core logic that gives an indication when the feedback clock has locked
onto the reference clock both in phase and frequency.
Altera recommends using the areset and locked signals in your designs to control
and observe the status of your PLL.
PLL reconfiguration or clock switchover is enabled in the design
Phase relationships between the PLL input and output clocks must be maintained
after a loss-of-lock condition
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
4–25