DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 490

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–34
Figure 4–24. Rate Match Deletion in GIGE Mode
Stratix V Device Handbook Volume 3: Transceivers
rx_rmfifodatadeleted
dataout
datain
Receiver synchronization is indicated on the rx_syncstatus port when the word
aligner status port is enabled or on the register bit using the Avalon Memory Mapped
Management Interface for each channel. A high on the rx_syncstatus port indicates
that the lane is synchronized; a low on the rx_syncstatus port indicates that the lane
has fallen out of synchronization. The receiver loses synchronization when it detects
four invalid code groups separated by less than three valid code groups or when it is
reset. It would take four consecutive valid code groups in order to reduce the error
count by one.
Clock Compensation Using the Rate Match FIFO
In GIGE mode, the rate match FIFO is capable of compensating for up to ±100 PPM
(200 PPM total) difference between the upstream transmitter and the local receiver
reference clock. The GIGE protocol requires the transmitter to send idle ordered sets
/I1/ (/K28.5/D5.6/) and /I2/ (/K28.5/D16.2/) during inter-packet gaps adhering to
the rules listed in the IEEE 802.3 specification.
The rate match operation begins after the synchronization state machine in the word
aligner indicates synchronization is acquired by driving the rx_syncstatus signal
high. The rate matcher silently deletes or inserts both symbols (/K28.5/ and /D16.2/)
of the /I2/ ordered sets even if it requires deleting only one symbol to prevent the
rate match FIFO from overflowing or under-running. It can insert or delete as many
/I2/ ordered sets as necessary to perform the rate match operation.
Two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted, indicating rate match
FIFO deletion and insertion events, respectively, are forwarded to the FPGA fabric.
Both the rx_rmfifodatadeleted and rx_rmfifodatainserted flags are asserted for
two clock cycles for each deleted and inserted /I2/ ordered set, respectively.
Figure 4–24
required to be deleted. Because the rate match FIFO can only delete /I2/ ordered set,
it deletes two /I2/ ordered sets (four symbols deleted).
Dx.y
Dx.y
shows an example of rate match FIFO deletion where three symbols are
First /I2/ Skip Ordered Set
K28.5
K28.5
D16.2
D16.2
/I2/ SKIP Symbol Deleted
Second /I2/ Skip Ordered Set
Dx.y
K28.5
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
D16.2
K28.5
Third /I2/ Skip Ordered Set
D16.2
May 2011 Altera Corporation
Dx.y
GIGE