DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 290

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

9–10
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
1
Table 9–6. DCLK-to-DATA[] Ratio
If the DCLK-to-DATA[] ratio is greater than 1, at the end of configuration, you can only
stop the DCLK (DCLK-to-DATA[] ratio – 1) clock cycles after the last data is latched into
the Stratix V device.
Figure 9–1
and a MAX II device for single device configuration.
Figure 9–1. Single Device FPP Configuration Using an External Host
Notes to
(1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix V device. V
(2) You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed another device's nCE pin.
(3) The MSEL pin settings vary for different data width, configuration voltage standards, and POR delay. To connect MSEL,
(4) If you use FPP ×8, use DATA[7..0]. If you use FPP ×16, use DATA[15..0].
FPP ×16
FPP ×32
Note to
(1) Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the data rate in bytes
Configuration
high enough to meet the V
up all configuration system I/Os with V
refer to
per second (Bps), or words per second (Wps). For example, in FPP ×16 when the DCLK-to-DATA[] ratio is 2, the
DCLK frequency must be 2 times the data rate in Wps. Stratix V devices use the additional clock cycles to decrypt
and decompress the configuration data.
Scheme
Table
Figure
Table 9–4 on page
shows the configuration interface connections between the Stratix V device
9–6:
9–1:
(MAX II Device or
Microprocessor)
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
External Host
ADDR DATA[7..0]
Disabled
Disabled
Enabled
Enabled
Disabled
Disabled
Enabled
Enabled
Memory
IH
9–7.
specification of the I/O on the device and the external host. Altera recommends powering
Decompression
(Note 1)
CCPGM
.
10 kΩ
V
(Part 2 of 2)
CCPGM
(1) V
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
CCPGM
Design Security
GND
10 kΩ
(1)
CONF_DONE
nSTATUS
nCE
nCONFIG
DCLK
DATA[31..0]
Stratix V Device
Fast Passive Parallel Configuration
May 2011 Altera Corporation
MSEL[4..0]
(4)
nCEO
DCLK-to-DATA[]
N.C. (2)
CCPGM
(3)
Ratio
1
2
4
4
1
4
8
8
must be