DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 480

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–24
Figure 4–16. Transceiver Clocking Configuration in a PIPE ×1 Configuration
Note to
(1) Only available in the central clock dividers of channel 1 and channel 4 in a transceiver bank.
Stratix V Device Handbook Volume 3: Transceivers
Figure
tx_coreclk
rx_coreclkin
tx_clkout
Transceiver Clocking
Fabric
FPGA
4–16:
This section describes the transceiver clocking configurations for PIPE.
PIPE ×1 Configuration
Figure 4–16
The serial clock is provided by the CMU PLL in a channel different from that of the
data channel. The local clock divider block in the data channel generates a parallel
clock from this high-speed clock and distributes both clocks to the PMA and PCS of
the data channel.
CMU PLL
CMU PLL
(From the ×1 Clock Lines)
shows the transceiver clocking configuration in a PIPE ×1 configuration.
Serial Clock
Central/ Local Clock Divider
Central/ Local Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
/2
/2
Clock Divider
Clock Divider
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
Parallel and Serial Clocks
(To the ×6 clock lines) (1)
Parallel and Serial Clocks
(To the ×6 clock lines) (1)
Parallel Clock (from the clock divider)
Parallel Clock (Recovered)
Transmitter Standard PCS
Receiver Standard PCS
PCI Express (PCIe)—Gen1 and Gen2
To the Transmitter Channel
Transmitter PMA
Parallel Clock
Serial Clock
Parallel and Serial Clocks
May 2011 Altera Corporation
Recovered
Receiver PMA
Clocks
Reference
Clock
Input
×1 Clock Line