DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 181

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 5: I/O Features in Stratix V Devices
I/O Banks
I/O Banks
Figure 5–1. I/O Banks for Stratix V Devices—Preliminary
May 2011 Altera Corporation
Bank 8A
Bank 3A
Figure 5–1
devices contain true differential input and output buffers and dedicated circuitry to
support differential I/O standards. Each I/O bank in Stratix V devices supports a
high-performance external memory interface. The I/O pins are organized in pairs to
support differential I/O standards. Each I/O pin pair can support both differential
input and output buffers.
Bank 8B
Bank 3B
Bank 3C
Bank 8C
shows the I/O banks in Stratix V devices. All I/O banks in Stratix V
This is a top view of the silicon die that corresponds to a reverse view for
flip chip packages. This figure illustrates the highest density for Stratix V devices.
More information about other Stratix V devices bank locations will be
available in future releases of the Stratix V device pin-out files.
Bank 3D
Bank 8D
Bank 8E
Bank 3E
Bank 7E
Bank 4E
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Bank 7D
Bank 4D
Bank 7C
Bank 4C
Bank 7B
Bank 4B
Bank 7A
Bank 4A
5–5