DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 493

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
XAUI
XAUI
May 2011 Altera Corporation
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1
To enable the use of the ATX PLL, a minimum base data rate of 2.5 Gbps must be
selected in the Custom PHY IP GIGE Preset to generate the 1.25 GHz clock for each
of the GIGE transceiver channel local clock dividers. In addition, the ATX PLL must
also be selected in the Quartus II Assignment Editor.
Figure 4–27. Channel Placement Guidelines in a GIGE Configuration
This section describes XAUI link implementation using Stratix V transceivers. It
provides the transceiver channel datapath description, clocking, and channel
placement guidelines when configured in a XAUI configuration.
In the MegaWizard Plug-In Manager, you can implement a XAUI link. Under
Ethernet in the Interfaces menu, select the XAUI PHY IP core. Currently, the XAUI
PHY IP core implements the XAUI PCS in soft logic.
For more information about the XAUI PHY IP core, see the
Core User
Within a Transceiver Bank:
When you use a CMU PLL:
Guide.
GIGE Ch 3
GIGE Ch 2
GIGE Ch 1
GIGE Ch 0
GIGE Ch 2
GIGE Ch 1
GIGE Ch 0
GIGE Ch 4
CMU PLL
GIGE Ch 3
GIGE Ch 4
CMU PLL
When you use an ATX PLL:
Within a Transceiver Bank:
Stratix V Device Handbook Volume 3: Transceivers
GIGE Ch 4
GIGE Ch 3
GIGE Ch 2
GIGE Ch 1
GIGE Ch 0
GIGE Ch 5
GIGE Ch 2
GIGE Ch 1
GIGE Ch 0
GIGE Ch 5
GIGE Ch 4
GIGE Ch 3
Altera Transceiver PHY IP
4–37