DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 268

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

7–24
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Delay Chain
The output path is designed to route combinatorial or registered single data rate
(SDR) outputs and full-rate or half-rate DDR outputs from the FPGA core. Half-rate
data is converted to full-rate with the HDR block, clocked by the half-rate clock from
the PLL. The resynchronization registers are also clocked by the same 0° system clock,
except in the DDR3 SDRAM interface. In DDR3 SDRAM interfaces, the leveling
registers are clocked by the write-leveling clock.
For more information about the write-leveling delay chain, refer to
Circuitry” on page
The output-enable path has a structure similar to the output path. You can have a
combinatorial or registered output in SDR applications and you can use half-rate or
full-rate operation in DDR applications. Also, the output-enable path’s
resynchronization registers have a structure similar to the output path registers,
ensuring that the output-enable path goes through the same delay and latency as the
output path.
Stratix V devices have run-time adjustable delay chains in the I/O blocks and the DQS
logic blocks. You can control the delay chain setting through the I/O or the DQS
configuration block output.
Figure 7–14. Delay Chain
Every I/O block contains the following:
■
■
■
■
Two delay chains in series between the output registers and output buffer
Two delay chains between the input buffer and input register
Two delay chains between the output enable and output buffer
Two delay chains between the R
7–20.
datain
Figure 7–14
T
delayctrlin [7..0]
OCT enable-control register and output buffer
shows the delay chain ports.
Chapter 7: External Memory Interfaces in Stratix V Devices
Δt
Stratix V External Memory Interface Features
dataout
May 2011 Altera Corporation
“Leveling