DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 435
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
- Current page: 435 of 530
- Download datasheet (16Mb)
Chapter 2: Transceiver Clocking in Stratix V Devices
Internal Clocking
May 2011 Altera Corporation
Figure 2–15. Five Channels Configured in Bonded Configuration
Notes to
(1) Serial clock from the ×1 clock lines.
(2) For channel 4, you cannot use the CDR for the receiver because the channel PLL is being used as a CMU PLL.
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Figure
CMU PLL
CMU PLL
CMU PLL
CMU PLL
CMU PLL
CMU PLL
Parallel Clock
Serial Clock
Parallel and Serial Clocks
2–15:
(1)
(1)
(1)
(1)
(1)
(1)
Local Clock Divider
Central Clock Divider
Local Clock Divider
Local Clock Divider
Central Clock Divider
Local Clock Divider
Receiver PCS
Receiver PCS
Receiver PCS
Receiver PCS
Receiver PCS
Receiver PCS
Clock Divider
Clock Divider
Clock Divider
Clock Divider
Clock Divider
Clock Divider
Deserializer
Deserializer
Deserializer
Deserializer
Deserializer
Deserializer
Stratix V Device Handbook Volume 3: Transceivers
Receiver PMA
Receiver PMA
Receiver PMA
Receiver PMA
Receiver PMA
Receiver PMA
To Transmitter Channel
To Transmitter Channel
To Transmitter Channel
To Transmitter Channel
To Transmitter Channel
To Transmitter Channel
Reference
Reference
Reference
Reference
Reference
Reference
CDR
CDR
CDR
CDR
CDR
CDR
(2)
Clock
Clock
Clock
Clock
Clock
Clock
Input
Input
Input
Input
Input
Input
×6 Clock Lines
×1 Clock Lines
2–19
Related parts for DK-DEV-5SGXEA7/ES
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: