DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 356

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

11–6
Boundary-Scan Description Language Support
Document Revision History
Table 11–4. Document Revision History
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
May 2011
December 2010
July 2010
Date
f
f
Version
The boundary-scan description language (BSDL), a subset of VHDL, provides a
syntax that allows you to describe the features of an IEEE Std. 1149.6 BST-capable
device that can be tested. You can test software development systems, then use the
BSDL files for test generation, analysis, and failure diagnostics.
For more information about BSDL files for IEEE Std. 1149.6-compliant Stratix V
devices, refer to the
You can also generate BSDL files (pre-configuration and post-configuration) for
IEEE Std. 1149.6-compliant Stratix V devices with the Quartus
version 10.0 SP1 and later. For more information about the procedure to generate
BSDL files using the Quartus II software, refer to the
page on the Altera website.
Table 11–4
1.2
1.1
1.0
Chapter moved to volume 2 for the 11.0 release.
Updated
No changes to the content of this chapter for the Quartus II software 10.1.
Initial release.
lists the revision history for this chapter.
Table
11–1.
IEEE 1149.6 BSDL Files
Chapter 11: JTAG Boundary-Scan Testing in Stratix V Devices
Changes
page on the Altera website.
Boundary-Scan Description Language Support
BSDL Files Generation in QII
®
May 2011 Altera Corporation
II software