DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 193
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
- Current page: 193 of 530
- Download datasheet (16Mb)
Chapter 5: I/O Features in Stratix V Devices
OCT Support and I/O Termination Schemes
Table 5–11. Selectable I/O Standards for OCT With and Without Calibration (Part 1 of 2)
May 2011 Altera Corporation
3.3V LVTTL/LVCMOS
2.5-V LVCMOS
1.8-V LVCMOS
1.2-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL15 Class I
SSTL15 Class II
HSTL 1.8 Class I
HSTL 1.8 Class II
HSTL 1.5 Class I
HSTL 1.5 Class II
HSTL 1.2 Class I
HSTL 1.2 Class II
SSTL15
SSTL135
SSTL125
SSTL12
HSUL 1.2
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
Differential SSTL15 Class I
Differential SSTL15 Class II
Differential HSTL 1.8 Class I
Differential HSTL 1.8 Class II
Differential HSTL 1.5 Class I
Differential HSTL 1.5 Class II
Differential HSTL 1.2 Class I
I/O standards
Table 5–11
calibration on different I/O standards.
lists the input and output termination for OCT with and without
OCT Setting, R
34.3, 40, 48, 60, 80
Uncalibrated R
25, 34, 40, 50
40, 60, 240
34, 40
34, 40
25/50
25/50
25/50
25/50
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
Output Termination
s
()
s
Setting, R
Calibrated R
25, 34, 40, 50
34, 40, 48, 60, 80
40, 60, 240
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
34, 40
34, 40
25/50
25/50
25/50
25/50
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
(2)
s
()
(2)
(2)
s
(2)
OCT
(2)
(1)
R
20, 30, 40, 60, 120
20, 30, 40, 60, 120
20, 30, 40, 60, 120
Input Termination
T
OCT Setting, R
60, 120
()
—
—
—
—
50
50
50
50
50
50
50
50
50
50
50
50
(2)
(2)
(2)
(2)
50
50
50
50
50
50
50
50
50
50
50
(2)
T
V
0.675
0.625
REF
1.25
1.25
0.75
0.75
0.75
0.75
0.75
1.25
1.25
0.75
0.75
0.75
0.75
0.9
0.9
0.9
0.9
0.6
0.6
0.6
0.6
0.9
0.9
0.9
0.9
0.6
—
—
—
—
(V)
V
1.35
1.25
5–17
2.5
1.8
1.2
2.5
2.5
1.8
1.8
1.5
1.5
1.8
1.8
1.5
1.5
1.2
1.2
1.5
1.2
1.2
2.5
2.5
1.8
1.8
1.5
1.5
1.8
1.8
1.5
1.5
1.2
(V)
CCIO
3
Related parts for DK-DEV-5SGXEA7/ES
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: