DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 195
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
- Current page: 195 of 530
- Download datasheet (16Mb)
Chapter 5: I/O Features in Stratix V Devices
OCT Support and I/O Termination Schemes
Figure 5–6. Dynamic R
May 2011 Altera Corporation
50 Ω
50 Ω
Transmitter
Receiver
Dynamic OCT
Stratix V devices support dynamic R
banks.
Dynamic R
disabled when it acts as a driver. Similarly, dynamic R
bidirectional I/O acts as a driver and is disabled when it acts as a receiver. This
feature is useful for terminating any high-performance bidirectional path because
signal integrity is optimized depending on the direction of the data.
Altera recommends using the new I/O standards for the DDR3 memory interface
with dynamic OCT schemes. These I/O standards save board space by reducing the
number of external termination resistors used.
Using dynamic OCT also helps save power because device termination is internal
instead of external. Termination only switches on during input operation, thus
drawing less static power.
T
OCT in Stratix V Devices
Stratix V OCT
Stratix V OCT
Figure 5–6
T
V
V
GND
GND
OCT is enabled only when the bidirectional I/O acts as a receiver and is
CCIO
CCIO
100 Ω
100 Ω
100 Ω
100 Ω
shows the termination schemes supported in Stratix V devices.
Z
Z
0
0
= 50 Ω
= 50 Ω
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
S
and R
T
V
V
GND
GND
OCT for bidirectional I/Os in all I/O
CCIO
CCIO
100 Ω
100 Ω
100 Ω
100 Ω
Stratix V OCT
Stratix V OCT
S
OCT is enabled only when the
Transmitter
Receiver
50 Ω
50 Ω
5–19
Related parts for DK-DEV-5SGXEA7/ES
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: