DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 512

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–10
Figure 5–8. Datapath for Custom Configurations with the Standard PCS
Stratix V Device Handbook Volume 3: Transceivers
tx_coreclk
rx_coreclk
rx_clkout
tx_clkout
Fabric
FPGA
CMU PLL
(From the ×1 Clock Lines)
Serial Clock
Figure 5–8
the standard PCS. The options available at different speeds are shown in
through
The standard PCS datapath offers flexibility by allowing you to modify, enable, or
disable blocks based on your requirements.
Central/ Local Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Figure
shows the complete datapath for custom transceiver configurations with
5–12.
/2
Transmitter PCS
/2
Receiver PCS
Clock Divider
Chapter 5: Transceiver Custom Configurations in Stratix V Devices
Parallel and Serial Clocks
(Only from the Central Clock Divider)
Standard PCS Custom and Low Latency Configurations
May 2011 Altera Corporation
Parallel Clock
Serial Clock
Parallel and Serial Clock
Transmitter PMA
Receiver PMA
Figure 5–9