DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 150
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
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Table 4–3. Clock Input Pin Connectivity to the RCLK Networks (Part 1 of 3)—Preliminary
RCLK
[58,59,60,61,62,
63,64,68,85,89]
RCLK
[58,59,60,61,62,
63,65,69,86,90]
RCLK
[58,59,60,61,62,
63,66,70,87,91]
RCLK
[58,59,60,61,62,
63,67,88]
RCLK
[20,24,28,30,34,
38]
RCLK
[21,25,29,31,35,
39]
RCLK [22,26,32,36] — — — — — — v —
RCLK [23,27,33,37] — — — — — — — v
RCLK
[52,53,54,55,56,
57,71,75,78,82]
RCLK
[52,53,54,55,56,
57,72,76,79,83]
RCLK
[52,53,54,55,56,
57,73,77,80,84]
Clock Resources
Table 4–3
can drive two adjacent RCLK networks to create a dual-regional clock network.
v
—
— —
— — —
— — — — v — — —
— — — — — v — —
— — — — — — — —
— — — — — — — —
— — — — — — — —
0
— — — — — — —
v
1
lists the connectivity between the dedicated clock input pins and RCLKs in Stratix V devices. A given clock input pin
v
— — — — — —
2
— — — — —
v
3
— — — —
4
5
6
7
v
—
—
—
—
—
—
—
—
(1)
—
—
8
—
—
—
—
—
—
—
—
—
v
—
(1)
9
10
—
—
—
—
—
—
—
—
—
—
v
(1)
11
—
—
—
—
—
—
—
—
—
—
—
12
—
—
—
—
—
—
—
—
—
—
—
CLK (p/n pins)
13
—
—
—
—
—
—
—
—
—
—
—
14
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
16 17 18 19 20 21 22 23
— — — — — — — —
— — — — — — — —
— — — — — — — —
— — — — — — — —
— — — — — — — —
— — — — — — — —
— — — — — — — —
— — — — — — — —
— — — — — — — —
— — — — — — — —
— — — — — — — —
24
—
—
—
—
—
—
—
—
—
—
—
25
—
—
—
—
—
—
—
—
—
—
—
26
—
—
—
—
—
—
—
—
—
—
—
27
—
—
—
—
—
—
—
—
—
—
—
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