DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 137

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 3: Variable Precision DSP Blocks in Stratix V Devices
Operational Mode Descriptions
Figure 3–20. 18-bit Systolic FIR Mode with Two Dynamic Inputs for Stratix V Devices
May 2011 Altera Corporation
COEFSELA[2..0]
COEFSELB[2..0]
datab_0[17..0]
dataa_1[17..0]
dataa_0[17..0]
datab_1[17..0]
Systolic FIR Mode
18
18
18
18
3
3
Stratix V variable precision DSP blocks support 18-bit or 27-bit systolic FIR structures.
Each input of the multiplier can come from three different sets of sources. They can be
from two dynamic inputs, one dynamic input and one coefficient input, or one
coefficient input and one pre-adder output. You can implement the 27-bit systolic FIR
mode using 27-bit multiplier with chainout feature enabled. The chainout output for
18-bit systolic FIR mode is 44-bits whereas for 27-bit systolic FIR mode is 64-bit.
Figure 3–20
Pre-Adder
Pre-Adder
+/-
+/-
shows the 18-bit systolic FIR with two dynamic inputs.
Coefficient
Coefficient
Internal
Internal
Registers
Systolic
Mult_H
Mult_L
x
x
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
18-bit Systolic FIR
Adder
+/-
+/-
chainin[43..0]
Register
Systolic
Chainout adder/
accumulator
+
chainout[43..0]
3–21
37
Result[43..0]