DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 222

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

6–8
Figure 6–6. Stratix V Serializer Bypass
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In DDR mode, tx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE.
(3) In SDR and DDR modes, the data width to the IOE is 1 and 2 bits, respectively.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Figure
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
6–6:
tx_coreclock
tx_coreclock
180° (edge or center aligned). The fractional PLLs provide additional support for
other phase shifts in 45° increments. These settings are made statically in the
Quartus II MegaWizard™ Plug-In Manager.
transmitter in clock output mode. In clock output mode, you can use an LVDS channel
as a clock output channel.
Figure 6–5. Stratix V Transmitter in Clock Output Mode
You can bypass the Stratix V serializer to support DDR (x2) and SDR (x1) operations
to achieve a serialization factor of 2 and 1, respectively. The I/O element (IOE)
contains two data output registers that can each operate in either DDR or SDR mode.
Figure 6–6
FPGA
Fabric
tx_in 2
shows the serializer bypass path.
FPGA
Fabric
Fractional PLL
(Note
DIN
DIN
Serializer
Serializer
3
DOUT
DOUT
1), (2),
Fractional
2
PLL
Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
(3)
IOE
Parallel
Transmitter Circuit
LVDS_LOAD_EN
diffioclk
LVDS Transmitter
Series
IOE supports SDR, DDR, or
Non-Registered Datapath
Figure 6–5
shows the Stratix V
May 2011 Altera Corporation
+
-
Differential Transmitter
Txclkout+
Txclkout–
tx_out