DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 504

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–2
Stratix V Device Handbook Volume 3: Transceivers
f
Figure 5–2
configuration. To select the custom transceiver configuration, use the Low Latency
PHY IP core. This IP core supports custom transceiver configurations that use the
standard PCS. You can enable this option in the IP core by enabling the select 10G
PCS option in the MegaWizard
For more information about the Low Latency PHY IP core, refer to the Low Latency
PHY IP Core chapter in the
The blocks shown as “Disabled” are not used, but incur latency. The blocks shown
as “Bypassed” are not used and do not incur any latency. The FPGA
fabric-to-transceiver interface frequency specified in
grade devices.
shows the different options available in the 10G Low Latency
Altera Transceiver PHY IP Core User
™
Plug-In Manager.
Chapter 5: Transceiver Custom Configurations in Stratix V Devices
Figure 5–2
Guide.
10G Low Latency Configuration
is for maximum speed
May 2011 Altera Corporation