DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 162

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–22
Figure 4–18. PLL Locations for 5SGSD6 and 5SGSD8 Devices
Note to
(1) Every index represents one fractional PLL in the device. The physical locations of the fractional PLLs correspond to the coordinates in the
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Quartus II software Chip Planner.
Figure
COR_X0_Y136
COR_X0_Y127
LR_X0_Y99
LR_X0_Y90
LR_X0_Y76
LR_X0_Y67
LR_X0_Y52
LR_X0_Y43
LR_X0_Y28
LR_X0_Y19
COR_X0_Y10
COR_X0_Y1
4–18:
Figure 4–18
4
4
4
4
4
4
CLK[20..23][p,n]
CLK[0..3][p,n]
shows the PLL locations for 5SGSD6 and 5SGSD8 devices.
4 Logical clocks
4
Pins
Logical clocks
Pins
CEN_X105_Y132
CEN_X105_Y123
CLK[16..19][p,n]
CEN_X105_Y11
CEN_X105_Y2
CLK[4..7][p,n]
5SGSD6
5SGSD8
4 Logical clocks
4 Logical clocks
Pins
Pins
(Note 1)
CLK[12..15][p,n]
CLK[8..11][p,n]
Chapter 4: Clock Networks and PLLs in Stratix V Devices
4 Logical clocks
4 Logical clocks
Pins
Pins
COR_X218_Y126
COR_X218_Y117
COR_X218_Y12
COR_X218_Y3
LR_X218_Y70
LR_X218_Y61
May 2011 Altera Corporation
CLK[24..27][p,n]
4
Stratix V PLLs
Pins