DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 154

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–14
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
f
1
1
When using the ALTCLKCTRL megafunction to implement dynamic clock source
selection, the inputs from the clock pins feed the inclk[0..1] ports of the multiplexer,
while the PLL outputs feed the inclk[2..3] ports. You can choose from among these
inputs using the CLKSELECT[1..0] signal.
For more information, refer to the
User
The mapping between the input clock pins, PLL counter outputs, and clock control
block inputs is as follows:
■
■
■
Corner PLLs cannot be used for dynamic clock control selection.
Figure 4–10. RCLK Control Block
Notes to
(1) When the device is in user mode, you can only set the clock select signals through a configuration file (.sof or .pof);
(2) The CLKn pin is not a dedicated clock input when used as a single-ended PLL clock input.
You can only control the clock source selection for the RCLK select block statically
using configuration bit settings in the configuration file (.sof or .pof) generated by the
Quartus II software.
inclk[0] and inclk[1]—can be fed by any of the four dedicated clock pins on the
same side of the Stratix V device
inclk[2]—can be fed by PLL counters C0 and C2 from the two center PLLs on the
same side of the Stratix V device
inclk[3]—can be fed by PLL counters C1 and C3 from the two center PLLs on the
same side of the Stratix V device
they cannot be dynamically controlled.
Guide.
Figure
4–10:
PLL Counter
Outputs
Clock Control Block (ALTCLKCTRL) Megafunction
2
CLKp
Pin
Enable/
Disable
RCLK
CLKn
Pin
Chapter 4: Clock Networks and PLLs in Stratix V Devices
(2)
Internal
Logic
Static Clock Select (1)
Internal
Logic
Clock Networks in Stratix V Devices
May 2011 Altera Corporation