DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 114

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–20
Figure 2–18. Mixed-Port Read-During-Write—Don’t Care Mode
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Power-Up Conditions and Memory Initialization
Power Management
q_b (asynch)
f
address_a
byteena_a
address_b
clk_a&b
wren_a
rden_b
data_a
Figure 2–18
behavior for don’t care mode.
Mixed-port read-during-write is not supported if you use two different clocks in a
dual-port RAM. The output value is unknown during a dual-clock mixed-port
read-during-write operation.
The M20K memory block outputs power up to zero (cleared), regardless of whether
the output registers are used or bypassed. MLABs power up to zero if the output
registers are used and power up reading the memory contents if the output registers
are not used. You must consider this when designing logic that might evaluate the
initial power-up values of the MLAB memory block. For Stratix V devices, the
Quartus II software initializes the RAM cells to zero unless there is a .mif specified.
All memory blocks support initialization with a .mif. You can create .mif files in the
Quartus II software and specify their use with the RAM MegaWizard Plug-In
Manager when instantiating a memory in your design. Even if a memory is
pre-initialized (for example, using a .mif), it still powers up with its outputs cleared.
For more information about .mif files, refer to the
Megafunction User Guide
Stratix V memory block clock-enables allow you to control the clocking of each
memory block to reduce AC power consumption. Use the read-enable signal to
ensure that read operations only occur when you require read operations. If your
design does not require read-during-write, you can reduce your power consumption
by deasserting the read-enable signal during write operations, or any period when no
memory operations occur.
The Quartus II software automatically places any unused memory blocks in
low-power mode to reduce static power.
shows a sample functional waveform of mixed-port read-during-write
AAAA
11
BBBB
and the
01
A0
A0
Quartus II
CCCC
10
XXXX (unknown data)
DDDD
Handbook.
Internal Memory (RAM and ROM)
Chapter 2: Memory Blocks in Stratix V Devices
EEEE
A1
A1
11
FFFF
May 2011 Altera Corporation
Design Considerations