DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 213

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 5: I/O Features in Stratix V Devices
Document Revision History
Document Revision History
Table 5–13. Document Revision History
May 2011 Altera Corporation
May 2011
January 2011
December 2010
July 2010
Date
1
If one I/O bank is using 3.0-V V
use 3.0-V V
If you are using an output or bidirectional pin with the 3.3 V-LVTTL/LVCMOS I/O
standard, you must adhere to this restriction manually with location assignments.
Table 5–13
Version
1.3
1.2
1.1
1.0
lists the revision history for this chapter.
CCPD
■
■
■
■
■
■
Updated Table 5–2.
No changes to the content of this chapter for the Quartus II software 10.1.
Initial release.
.
Chapter moved to volume 2 for the 11.0 release.
Added
Updated
Termination”, and
Updated
Updated
Figure
Minor text edits.
5–20, and
Table
“Single-Ended I/O Standards
Table 5–3
Figure
5–4,
5–1,
CCPD
Figure
Table
“V
and
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
CCPD
Figure
, other I/O banks in the same group must also
Table
5–5,
5–21.
Restriction”
5–8,
Table
5–11.
Figure
Changes
5–6,
Termination”,
sections.
Table
5–9,
Figure
5–7, and
5–10,
“Differential I/O Standards
Table
Figure
5–8.
5–17,
5–37