DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 57
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
- Current page: 57 of 530
- Download datasheet (16Mb)
Chapter 2: DC and Switching Characteristics for Stratix V Devices
I/O Timing
Table 2–34. IOE Programmable Delay for Stratix V Devices—Preliminary
May 2011 Altera Corporation
Notes to
(1) Pending the Quartus II software extraction.
(2) You can set this value in the Quartus II software by selecting D1, D2, D3,D5, and D6 in the Assignment Name column.
(3) Minimum offset does not include the intrinsic delay.
Parameter
D1
D2
D3
D5
D6
(2)
Table
Programmable IOE Delay
Programmable Output Buffer Delay
2–34:
Available
Settings
63
31
63
31
7
Table 2–34
Table 2–35
of the output buffer. The default delay is 0 ps.
Table 2–35. Programmable Output Buffer Delay for Stratix V Devices—Preliminary
D
Notes to
(1) Pending the Quartus II software extraction.
(2) You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay
OUTBUF
Offset
Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the
Output Buffer Delay assignment.
Min
0
0
0
0
0
Table
Symbol
(3)
lists the Stratix V IOE programmable delay settings.
lists the delay chain settings that control the rising and falling edge delays
2–35:
Industrial
0.471
0.274
1.668
0.493
0.273
Fast Model
Rising and/or falling edge
delay
Commercial
0.514
0.274
1.735
0.474
0.258
Parameter
0.800
0.423
2.830
0.835
0.463
C2
Stratix V Device Handbook Volume 1: Overview and Datasheet
(Note 1)
0.843
0.456
2.985
0.882
0.488
C3
0.918
0.501
3.252
0.960
0.532
0 (default)
Typical
C4
Slow Model
100
150
50
0.850
0.453
3.007
0.888
0.492
I3
0.924
0.498
3.274
0.966
0.536
I4
(Note
Unit
ps
ps
ps
ps
1),
Unit
2–29
ns
ns
ns
ns
ns
(2)
Related parts for DK-DEV-5SGXEA7/ES
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-DEV-2AGX125N](/photos/28/41/284154/dk-dev-2agx125n_tmb.jpg)
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
![DK-DEV-3CLS200N](/photos/9/24/92409/dk-dev-3cls200n_tmb.jpg)
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SE530N](/photos/28/41/284157/dk-dev-4se530n_tmb.jpg)
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
![DK-DEV-2AGX260N](/photos/28/41/284175/dk-dev-2agx260n_tmb.jpg)
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
![DK-DEV-5M570ZN](/photos/18/31/183180/dk-dev-5m570zn_tmb.jpg)
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
![DK-DEV-3SL150N](/photos/9/20/92079/dk-dev-3sl150n_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SGX230N](/photos/28/41/284156/dk-dev-4sgx230n_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
![DK-DEV-1AGX60N](/photos/9/31/93181/mfgdk-dev-1agx60n_tmb.jpg)
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
![DK-DEV-4CGX150N](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SGX530N](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: