DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 82

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–4
Figure 1–4. LAB-Wide Control Signals
Adaptive Logic Modules
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Dedicated Row LAB Clocks
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
The LAB row clocks [5..0] and LAB local interconnects generate the LAB-wide control
signals. The MultiTrack interconnect’s inherent low skew allows clock and control
signal distribution in addition to data. The MultiTrack interconnect consists of
continuous, performance-optimized routing lines of different lengths and speeds
used for inter- and intra-design block connectivity.
The ALM is the basic building block of logic in the Stratix V architecture. It provides
advanced features with efficient logic utilization. Each ALM contains a variety of
LUT-based resources that can be divided between two combinational adaptive LUTs
(ALUTs) and four registers. With up to eight inputs for the two combinational ALUTs,
one ALM can implement various combinations of two functions. This adaptability
allows an ALM to be completely backward-compatible with four-input LUT
architectures. One ALM can also implement any function with up to six inputs and
certain seven-input functions.
6
6
6
labclk0
clock signals per LAB.
There are two unique
or asyncload
or labpreset
labclkena0
Chapter 1: Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices
labclk1
labclkena1
labclk2
labclkena2
syncload
labclr0
May 2011 Altera Corporation
labclr1
Adaptive Logic Modules
synclr