DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 509

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 5: Transceiver Custom Configurations in Stratix V Devices
10G Low Latency Configuration
Figure 5–6. 10G PCS Low Latency Datapath with the Gear Box Ratio of 40:66 or 40:50
Note to
(1) The clock source that provides the input reference clock to the fractional PLL (fPLL in
May 2011 Altera Corporation
tx_coreclk
rx_coreclk
Fabric
FPGA
high-speed clock for the serializer) must be the same. The transmitter and the receiver FIFOs can only compensate for phase differences.
Therefore, the same clock source ensures 0 PPM between the read and write clocks of the FIFOs.
Input Reference Clock (1)
Figure
Using coreclks
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fPLL
5–6:
f
CMU PLL
For the receive side, enable the rx_coreclk port and connect the fractional PLL output
to the rx_coreclk port. The RX FIFO operates as a phase compensation FIFO.
Therefore, the read and write side of the RX FIFO must have a 0 PPM difference. This
requires that the receive side and the upstream transmitter are clocked by the same
clock source (synchronous systems).
The tx_coreclk and rx_coreclk ports offer the flexibility to use the tx_clkout and
rx_clkout from one channel to clock the TX and RX FIFOs multiple channels.
For more information about the core clocking scheme, refer to the following sections
in the Transceiver Clocking for Stratix V Devices chapter:
■
■
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(From the ×1 Clock Lines)
“User-Selected Transmitter Datapath Interface Clock”
“User-Selected Receiver Datapath Interface Clock”
Serial Clock
Central/ Local Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Clock Divider
Figure
Parallel and Serial Clocks
(Only from the Central Clock Divider)
5–6) and the CMU PLL (the CMU PLL generates the
Stratix V Device Handbook Volume 3: Transceivers
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Transmitter 10G PCS
Receiver 10G PCS
40
40
Transmitter PMA
Parallel Clock
Serial Clock
Parallel Clock and Serial Clock
Receiver PMA
Input Reference
Clock
5–7