DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 123

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 3: Variable Precision DSP Blocks in Stratix V Devices
Variable Precision DSP Block Resource Descriptions
May 2011 Altera Corporation
Pre-Adder and Coefficient Select
1
Figure 3–3. Input Register of a Variable Precision DSP Block in 27 x 27 Mode for Stratix V
Devices
Note to
(1)
The pre-adder supports both addition and subtraction. There are two 18-bit
pre-adders in each variable precision DSP block. You can configure these two
pre-adders as two independent 18-bit adders for 18-bit applications, or a 25-bit adder
for 27-bit applications.
The Stratix V variable precision DSP block has the flexibility of selecting the
multiplicand from either the dynamic input or internal coefficient. The internal
coefficient can support up to eight constant coefficients for the multiplicands in 18-bit
and 27-bit applications. When you enable the internal coefficient feature, the
COEFSELA/COEFSELB are used to control the dynamic selection of the coefficient
multiplexer.
In 18-bit applications, you must enable the coefficient feature when the pre-adder
feature is enabled. In 27-bit applications, you can use the coefficient feature and
pre-adder feature independently. In 27-bit applications with the pre-adder feature
enabled, the input data width is restricted to 22 bits if the multiplicand input comes
from dynamic input due to input limitations. If the multiplicand input comes from
internal coefficient, the data width of the input is 27 bits.
When you enable the pre-adder feature, all input data and multipliers must have the
same clock setting.
Figure 3–3
Figure
3–3:
shows only the data registers. Registers for the control signals are not shown.
datab_0[26..0]
dataa_0[26..0]
datac_0[24..0]
scanin[26..0]
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
scanout[26..0]
ENA[2..0]
CLK[2..0]
ACLR[0]
3–7