DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 310

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

9–30
Figure 9–18. PS Configuration Timing Waveform
Notes to
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When
(2) After power-up, the Stratix V device holds nSTATUS low for the time of the POR delay.
(3) After power-up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(5) DATA0 is available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings in the Device and Pins
(6) To ensure a successful configuration, send the entire configuration data to the Stratix V device. CONF_DONE is released high after the Stratix V
(7) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low.
Table 9–12. PS Timing Parameters for Stratix V Devices
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
t
t
t
t
t
CF2CD
CF2ST0
CFG
STATUS
CF2ST1
Symbol
nCONFIG is pulled low, a reconfiguration cycle begins.
Option.
device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin
initialization and enter user mode.
Figure
PS Configuration Timing
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS high
9–18:
1
CONF_DONE (3)
INIT_DONE (7)
nSTATUS (2)
nCONFIG
In
and complete the configuration and enter user mode at the same time.
To configure the PS multi-device with a single .sof, as shown in
Stratix V devices in the chain must be in the same package and density.
Figure 9–18
device or microprocessor as an external host.
Table 9–12
User I/O
DATA0
DCLK
Figure
9–17, because both nCE pins are tied to GND, both devices in the chain begin
t
t
CFG
CF2CD
lists the PS configuration timing parameters for Stratix V devices.
Parameter
shows the timing waveform for a PS configuration when using a MAX II
t
CF2ST1
t
CF2ST0
t
CF2CK
t
ST2CK
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
t
Bit 0 Bit 1 Bit 2 Bit 3
STATUS
High-Z
t
CH
t
CLK
t
DSU
t
CL
t
DH
(Note 1)
(Note 1)
(Part 1 of 2)
(6)
Bit n
Minimum
268
—
—
—
2
t
CD2UM
User Mode
May 2011 Altera Corporation
Figure
(5)
Maximum
(4)
1,506
1,506
Passive Serial Configuration
600
600
—
(2)
(3)
9–17, all
Units
ns
ns
s
s
s