DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 269
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
- Current page: 269 of 530
- Download datasheet (16Mb)
Chapter 7: External Memory Interfaces in Stratix V Devices
Stratix V External Memory Interface Features
May 2011 Altera Corporation
Figure 7–15
Figure 7–15. Delay Chains in an I/O Block
octdelaysetting1
octdelaysetting2
shows the delay chains in an I/O block.
D5 OCT
D6 OCT
rtena
delay
delay
chain
chain
delay chain
delay chain
D5 output-
D6 output-
enable
enable
oe
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
padtoinputregisterdelaysetting
D6 Delay
outputdelaysetting2
delay
chain
delay chain
D1 Delay
padtoinputregisterrisefalldelaysetting[5..0]
outputdelaysetting1
D5 Delay
delay
chain
delay chain
Balancing
Rise/Fall
0
1
7–25
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