DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 198

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–22
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
OCT Calibration Block Modes of Operation
OCT calibration can occur in either power-up or user mode.
Power-Up Mode
In power-up mode, OCT calibration is automatically performed at power up.
Calibration codes are shifted to selected I/O buffers before transitioning to user
mode.
User Mode
In user mode, the OCTUSRCLK, ENAOCT, nCLRUSR, and ENASER signals are used to calibrate
and serially transfer calibration codes from each OCT calibration block to any I/O.
Table 5–12
descriptions.
Table 5–12. OCT Calibration Block Ports for User Control
OCTUSRCLK
ENAOCT
ENASER[7..0]
S2PENA_<bank#>
nCLRUSR
Signal Name
lists the user-controlled calibration block signal names and their
Clock for OCT block.
Enable OCT Calibration (Generated by user IP).
When ENOCT = 0, each signal enables the OCT serializer for the
corresponding OCT calibration block.
When ENAOCT = 1, each signal enables OCT calibration for the
corresponding OCT calibration block.
Serial-to-parallel load enable per I/O bank.
Clear user.
Description
Chapter 5: I/O Features in Stratix V Devices
May 2011 Altera Corporation
OCT Calibration