DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 445

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Transceiver Clocking in Stratix V Devices
FPGA Fabric-Transceiver Interface Clocking
Figure 2–22. Receiver Datapath Interface Clocking for Non-Bonded Channels
Note to
(1) If you use a rate matcher, the tx_clkout clock is used.
May 2011 Altera Corporation
Figure
Data and Status Logic
Data and Status Logic
Channel 0 Receiver
Channel 1 Receiver
2–22:
f
1
FPGA Fabric
For more information about interface clocking for each configuration, refer to the
clocking sections for each configuration in the
Stratix V Devices
You can clock the receiver datapath interface by using one of the following:
■
■
User-selection is provided to share the transceiver datapath interface clocks to reduce
GCLK, RCLK, and PCLK resource utilization in your design.
Quartus II Software-Selected Receiver Datapath Interface Clock
The Quartus II software automatically picks the appropriate clock from the FPGA
fabric to clock the receiver datapath interface.
datapath interface of two non-bonded channels clocked by their respective receiver
PCS clocks forwarded to the FPGA fabric.
rx_coreclkin[1]
rx_coreclkin[0]
Quartus II-selected receiver datapath interface clock
User-selected receiver datapath interface clock
chapter.
rx_clkout[0]/tx_clkout[0]
Receiver Data
Receiver Data
rx_clkout[1]/tx_clkout[1]
Compensation
Compensation
(1)
Phase
Phase
(1)
FIFO
FIFO
RX
RX
Figure 2–22
Transceiver Protocol Configurations in
Parallel Clock (Recovered Clock)
Parallel Clock (Recovered Clock)
Stratix V Device Handbook Volume 3: Transceivers
Receiver Data
Receiver Data
shows the receiver
Channel 1
Channel 0
2–29