DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 321

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Device Configuration Pins
Table 9–14. Configuration Pins Description (Part 3 of 3)
May 2011 Altera Corporation
MSEL[4..0]
nSTATUS
nCE
nCEO
nCONFIG
nCSO
nIO_PULLUP
AS_DATA0/ASDO
AS_DATA[3..1]
Notes to
(1) If the JTAG interface is not required on the board, you can disable the JTAG circuitry by connecting this pin to logic high. For instructions to
(2) This is a dual-purpose pin. This pin is available as an I/O if the associated option that enables this pin is turned off from the Configuration panel
(3) This is a dual-purpose pin. The state of this pin in the user mode depends on Dual-purpose Pins settings in the Device and Pins Option settings.
connect a JTAG chain with multiple voltages across the devices in the chain, refer to the
in the Device and Pins Option settings. For example, the DEV_OE is available as a user I/O if the Enable device-wide output enable option is
turned off.
Pin Name
(3)
Table
9–14:
Dedicated input pins. Five-bit configuration input that sets the Stratix V device configuration scheme.
For the appropriate connections, refer to
The MSEL[4..0] pins have internal 5-k
Dedicated open-drain bidirectional pin. The device drives nSTATUS low immediately after power-up
and releases it after the device exits POR. During user mode and regular configuration, this pin is
pulled high by an external 10-k
During configuration, the device drives this pin low to indicate an error during configuration. If an
external source drives the nSTATUS pin low during configuration or initialization, the target device
enters an error state. This mechanism is used during multi-device configuration setup. If one of the
devices in the chain has an error and pulls its nSTATUS pin low, it resets the entire chain.
Driving nSTATUS low after configuration and initialization completes does not affect the configured
device.
Dedicated active-low chip enable input pin. Driving this pin low allows configuration. Drives the
pin low during configuration, initialization, and user mode for all single-device configurations. For a
multi-device configuration, connect the nCE pin to GND or to the nCEO of the previous device in the
chain based on the recommendation in the respective configuration setup diagram.
Dual-purpose open-drain output pin. This pin drives low when device configuration completes. To use
this pin to feed the next device’s nCE pin in a multi-device chain, turn on Enable INIT_DONE output
option under Device and Pins Option, General panel in the Quartus II Software. In a single-device
configuration, this pin can be used as a regular I/O. In multi-device configuration, if this pin is not
feeding the nCE of the next device, you can use it as a regular I/O.
Dedicated input pin. A low pulse on this pin during configuration and user mode causes the device to
enter a reset state and tri-states all the I/O pins. A low-to-high logic starts a reconfiguration.
During JTAG programming, the nCONFIG status is ignored.
Dedicated output pin. Drives the control signal from the Stratix V device to the EPCS and EPCQ
devices in AS mode. After AS configuration completes, these pins are tri-stated with a weak pull-up
resistor.
Dedicated input pin. This input pin enables or disables the internal pull-up resistors on the user I/O
pins and dual purpose I/O pins (DATA[31..0], CLKUSR, INIT_DONE, DEV_OE, and
DEV_CLRN). A logic high turns off the weak internal pull-up resistors, while a logic low turns them
on.
This pin has an internal 5-k
Dedicated bidirectional data pin. In AS 1 and AS 4 configurations, ASDO is used to send the
operation command and addresses to the EPCS or EPCQ devices. During an AS 4 configuration, the
data is received on an AS_DATA0 and is synchronized to DCLK.
After AS configuration completes, this pin is tri-stated with a weak pull-up resistor.
Dedicated bidirectional data pins. During an AS configuration, the data is received on these pins and is
synchronized to DCLK.
After AS configuration completes, these pins are tri-stated with a weak pull-up resistor.
 pull-down resistor that is always active.

resistor.
Table 9–4 on page

Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Description
pull-down resistors that are always active.
JTAG Boundary Scan Testing
9–7.
chapter.
nCE
9–41