DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 45

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: DC and Switching Characteristics for Stratix V Devices
Switching Characteristics
Table 2–21. PLL Specifications for Stratix V Devices (Part 1 of 3)—Preliminary
May 2011 Altera Corporation
f
f
f
f
t
f
f
t
t
IN
INPFD
FINPFD
VCO
EINDUTY
OUT
OUT_EXT
OUTDUTY
FCOMP
Symbol
Core Performance Specifications
Input clock frequency (–2 speed grade)
Input clock frequency (–3 speed grade)
Input clock frequency (–4 speed grade)
Input frequency to the PFD
Fractional Input clock frequency to the PFD
PLL VCO operating range (–2 speed grade)
PLL VCO operating range (–3 speed grade)
PLL VCO operating range (–4 speed grade)
Input clock or external feedback clock input duty cycle
Output frequency for an internal global or regional clock
(–2 speed grade)
Output frequency for an internal global or regional clock
(–3 speed grade)
Output frequency for an internal global or regional clock
(–4 speed grade)
Output frequency for an external clock output
(–2 speed grade)
Output frequency for an external clock output
(–3 speed grade)
Output frequency for an external clock output
(–4 speed grade)
Duty cycle for an external clock output (when set to 50%)
External feedback clock compensation time
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), memory blocks, configuration, and JTAG specifications.
Clock Tree Specifications
Table 2–20
Table 2–20. Clock Tree Performance for Stratix V Devices—Preliminary
PLL Specifications
Table 2–21
commercial junction temperature range (0° to 85°C) and the industrial junction
temperature range (-40° to 100°C).
Periphery Clock
Regional Clock
Global and
Symbol
lists the clock tree specifications for Stratix V devices.
lists the Stratix V PLL specifications when operating in both the
Parameter
–2 Speed Grade
717
550
Performance
–3 Speed Grade
Stratix V Device Handbook Volume 1: Overview and Datasheet
700
500
Min
600
600
600
50
40
—
—
—
—
—
—
45
—
5
5
5
5
(Note 1)
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
—
–4 Speed Grade
500
500
800
700
650
717
700
500
800
667
533
1600
1400
1300
Max
325
133
60
55
10
(2)
(2)
(2)
(3)
(3)
(3)
(3)
(3)
(3)
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
ns
%
%
2–17