DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 469

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
Interlaken
Figure 4–9. Interlaken Single-Lane Configuration
May 2011 Altera Corporation
Fabric
FPGA
1-bit Ctrl/Data
tx_user_clk
1 bit Ctrl/Data
rx_user_clk
Transceiver Clocking and Channel Placement Guidelines
64
64
CMU PLL/ ATX PLL
(From the ×1 Clock Lines)
This section describes the transceiver clocking and channel placement guidelines for
the Interlaken protocol supported in Stratix V devices.
Transceiver Clocking
Current Interlaken protocol supports single-lane clocking (non-bonded
configurations) only.
single-lane Interlaken configuration.
A CMU PLL or ATX PLL may provide a clock to up to five Interlaken channels within
a transceiver bank of six channels.
Serial Clock
Central/ Local Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Figure 4–9
Paralell Clock (Recovered)
Paralell Clock
Clock Divider
shows the clocking resources available in a
Stratix V Device Handbook Volume 3: Transceivers
Transmitter 10G PCS
Receiver 10G PCS
40
40
Transmitter PMA
Receiver
Receiver PMA
Parallel Clock
Serial Clock
Parallel and Serial Clocks
4–13