DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 474

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–18
Stratix V Device Handbook Volume 3: Transceivers
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1
PIPE 2.0 Interface
In a PCIe configuration, each channel has a PIPE interface block that transfers data,
control, and status signals between the PHY-MAC layer and the transceiver channel
PCS and PMA blocks. The PIPE interface block complies with the PIPE 2.0
specification. If you use the PIPE hard IP block, the PHY-MAC layer is implemented
in the hard IP block. If you use a PIPE configuration, you must implement the
PHY-MAC layer using soft IP in the FPGA fabric.
The PIPE interface block is only used in a PIPE configuration and cannot be bypassed.
Besides transferring data, control, and status signals between the PHY-MAC layer
and the transceiver, the PIPE interface block implements the following functions
required in a PCIe-compliant physical layer device:
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PCI Express Gen2 (5 Gbps) Support
The PIPE configuration supports the following additional features when configured
for the 5 Gbps data rate:
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Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) Signal Rates
In a PIPE configuration, the PIPE MegaWizard
signal (pipe_rate) that is functionally equivalent to the RATE signal specified in the
PCIe specification. A low-to-high transition on this input signal (pipe_rate) initiates a
data rate switch from Gen1 to Gen2. A high-to-low transition on the input signal
initiates a data rate switch from Gen2 to Gen1. The signaling rate switch between
Gen1 and Gen2 is achieved by changing the transceiver datapath clock frequency
between 250 MHz and 500 MHz, while maintaining a constant, 16-bit width
transceiver interface.
For more information about using this input signal, and a timing diagram showing
the sequence of rate switch events and status signals, refer to the PCI Express PIPE
PHY IP Core chapter in the
state requirements when switching between Gen1 and Gen2 data rates, refer to the
PCIe Base Specification 2.0.
Forcing the transmitter buffer in the electrical idle state
Initiating the receiver detect sequence
Controlling the 8B/10B encoder disparity when transmitting compliance pattern
Managing the PCIe power states
Indicating the completion of various PHY functions; for example, receiver
detection and power state transitions on the pipe_phystatus signal
Encoding the receiver status and error conditions on the pipe_rxstatus[2:0]
signal, as specified in the PCIe specification
Dynamic switching between 2.5 Gbps and 5 Gbps signaling rate
Dynamic selection of transmitter margining for differential output voltage control
Dynamic selection of transmitter buffer de-emphasis of –3.5 dB and –6 dB
Altera Transceiver PHY IP Core User
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
™
Plug-In Manager provides an input
PCI Express (PCIe)—Gen1 and Gen2
Guide. For the power
May 2011 Altera Corporation