DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 295

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Fast Passive Parallel Configuration
Figure 9–5. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1
Notes to
(1) Use this timing waveform and parameters when the DCLK-to-DATA[]ratio is >1. To find out the DCLK-to-DATA[] ratio for your system, refer
(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
(3) After power-up, the Stratix V device holds nSTATUS low for the time as specified by the POR delay.
(4) After power-up, before and during configuration, CONF_DONE is low.
(5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(6) “r” denotes the DCLK-to-DATA[] ratio. For the DCLK-to-DATA[] ratio based on the decompression and the design security feature enable
(7) If needed, pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[31..0] pins prior to sending
(8) To ensure a successful configuration, send the entire configuration data to the Stratix V device. CONF_DONE is released high after the Stratix V
(9) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low.
Table 9–8. FPP Timing Parameters for Stratix V Devices When the DCLK-to-DATA[] Ratio is >1
May 2011 Altera Corporation
t
t
t
t
t
t
t
t
Symbol
CF2CD
CF2ST0
CFG
STATUS
CF2ST1
CF2CK
ST2CK
DSU
DATA[31..0] (8)
CONF_DONE
INIT_DONE
Table 9–6 on page
When nCONFIG is pulled low, a reconfiguration cycle begins.
settings, refer to
the first DCLK rising edge.
device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin
initialization and enter user mode.
nSTATUS (3)
nCONFIG
DCLK (6)
Figure
User I/O
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
DATA[] setup time before rising edge on DCLK
(9)
(4)
9–5:
Table 9–6 on page
t
t
9–9.
CF2CD
CFG
t
CF2ST1
t
CF2ST0
Figure 9–5
device or microprocessor as an external host. This waveform shows timing when the
DCLK-to-DATA[]ratio is more than 1.
Table 9–8
the DCLK-to-DATA[]ratio is more than 1.
t
CF2CK
t
ST2CK
t
STATUS
t
High-Z
DSU
1
9–9.
2
Word 0
lists the timing parameters for Stratix V devices for FPP configuration when
Parameter
t
DH
shows the timing waveform for FPP configuration when using a MAX II
r
t
CH
1
t
CL
2
t
Word 1
CLK
t
DH
r
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
(7)
Word 3
1
Minimum
1,506
268
5.5
—
—
—
2
2
(8)
Word (n-1)
r
(Note
1
Word n
2
1),
(Note
Maximum
t
1,506
1,506
CD2UM
(2)
600
600
—
—
—
—
1),
(3)
(3)
(2)
(5)
User Mode
User Mode
(Part 1 of 2)
Units
s
s
s
s
s
ns
ns
ns
9–15