DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 202
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
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5–26
Figure 5–13. SSTL I/O Standard Termination
Note to
(1) This is not applicable for SSTL-12, SSTL-15, SSTL-125, and SSTL-135 I/O standards.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Bi-Directional
OCT Transmit
OCT Receive
Termination
Termination
On-Board
External
OCT in
Pins
Figure
Stratix V
Series OCT 50 Ω
5–13:
OCT 50 Ω
Series
Transmitter
Transmitter
Transmitter
Stratix V
Figure 5–13
V
GND
CCIO
100 Ω
100 Ω
25 Ω
25 Ω
SSTL Class I
50 Ω
V
50 Ω
shows the details of SSTL I/O termination on Stratix V devices.
50 Ω
50 Ω
REF
V
V
50 Ω
REF
REF
50 Ω
V
TT
V
TT
(Note 1)
V
GND
CCIO
V
GND
CCIO
100 Ω
100 Ω
100 Ω
100 Ω
Receiver
Receiver
Receiver
Stratix V
OCT 50 Ω
Series
Parallel OCT
Stratix V
Stratix V
Series OCT 25 Ω
OCT 25 Ω
Series
Transmitter
Transmitter
Transmitter
Stratix V
V
GND
CCIO
100 Ω
100 Ω
Chapter 5: I/O Features in Stratix V Devices
25 Ω
25 Ω
V
TT
50 Ω
V
V
TT
TT
Termination Schemes for I/O Standards
50 Ω
SSTL Class II
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
V
REF
V
V
REF
50 Ω
REF
50 Ω
May 2011 Altera Corporation
V
V
TT
TT
V
GND
CCIO
V
GND
CCIO
100 Ω
100 Ω
100 Ω
100 Ω
Receiver
Receiver
Receiver
Stratix V
OCT 25 Ω
Series
Parallel OCT
Stratix V
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