DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 261

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Figure 7–6. Stratix V DQS Logic Block
Notes to
(1) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. For more information, refer to
(2) The dqsenable signal can also come from the Stratix V FPGA fabric.
Postamble
Enable
Figure
dqsenablein
zerophaseclk
DQS Postamble Circuit
DQS Logic Block
Postamble clock
7–6:
D Q
<bypass_output_register>
Each DQS/CQ and CQn pin is connected to a separate DQS logic block, which consists of the DQS delay chains, update enable
circuitry, and DQS postamble circuitry
0
1
enaphasetransferreg
D Q
leveling clk
DQS/CQ or
CQn Pin
Read-leveled
postamble clock
0
1
D Q
D Q
<delay_dqs_enable_by_half_cycle>
dqsin
DQS Enable
D Q
PRE
0
1
dqsenable
dqsenableout
(Figure
7–6).
Phase offset
settings from the
DQS phase-shift
circuitry
DQS delay
settings from the
DQS phase-shift
circuitry
offsetctrlin [6..0]
<use_alternate_input_for
first_stage_delay_control>
7
<dqs_offsetctrl_enable>
delayctrlin [6..0]
1
0
7
0
1
7
D
Q
Input Reference
Clock (1)
7
0
1
dqsin
7
DQS Delay Chain
D
Table 7–3 on page 7–11
Q
dqsupdateen
7
0
1
<dqs_ctrl_latches_enable>
7
Update
Enable
Circuitry
through
phasectrlin[1..0]
00
01
10
11
Table 7–6 on page
dqsbusout
7–13.