DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 79

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

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SV51002-1.2
Logic Array Blocks
Figure 1–1. LAB Structure for Stratix V Devices
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
May 2011
May 2011
SV51002-1.2
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
This chapter describes the features of the logic array blocks (LABs) in the Stratix
core fabric. LABs are made up of adaptive logic modules (ALMs) that you can
configure to implement logic functions, arithmetic functions, and register functions.
LABs and ALMs are the basic building blocks of the Stratix V device. ALMs provide
advanced features with efficient logic utilization and are completely
backward-compatible.
This chapter contains the following sections:
■
■
Each LAB consists of ten ALMs, various carry chains, shared arithmetic chains, LAB
Stratix V control signals, a local interconnect, and register chain connection lines. The
local interconnect transfers signals between ALMs in the same LAB. The direct link
interconnect enables the LAB to drive into the local interconnect of its left and right
neighbors. Register chain connections transfer the output of the ALM register to the
adjacent ALM register in the LAB. The Quartus
in the same LAB or adjacent LABs, allowing the use of local, shared arithmetic chain,
and register chain connections for performance and area efficiency.
the Stratix V LAB structure and the LAB interconnects.
R20
R4
“Logic Array Blocks” on page 1–1
“Adaptive Logic Modules” on page 1–4
Local Interconnect
1. Logic Array Blocks and Adaptive Logic
LAB
C4
from Either Side by Columns & LABs,
C12
Local Interconnect is Driven
and from Above by Rows
Row Interconnects of
Variable Speed and Length
Modules in Stratix V Devices
MLAB
®
II Compiler places associated logic
ALMs
Column Interconnects of
Variable Speed and Length
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Figure 1–1
shows
Subscribe
®
V