DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 117

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
SV51004-1.2
Variable Precision DSP Block Overview
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
May 2011
May 2011
SV51004-1.2
This chapter describes how the variable precision digital signal processing (DSP)
blocks in Stratix
high-performance DSP applications, such as radar systems that must support higher
resolution and multi-antenna architectures, wireless-base station channel cards for
MIMO processing, medical and test applications for very high-precision filtering, and
fast Fourier transforms (FFTs) functions.
You can configure a variable precision DSP block to implement one of several
operational modes to suit your application. The built-in pre-adder, coefficient bank,
multipliers, and adder/subtractor minimize the amount of external logic to
implement these functions, resulting in efficient resource usage, reduced power
consumption, improved performance, and data throughput for DSP applications.
A Stratix V variable precision DSP block maintains backward compatibility, so it can
efficiently support existing 18-bit DSP applications, such as high-definition video
processing, digital-up and down conversion, and multi-rate filtering.
This chapter contains the following sections:
■
■
■
■
■
Each Stratix V variable precision DSP block spans one logic array block (LAB) row
height.
The following are the architectural highlights of the Stratix V variable precision DSP
block:
■
■
■
■
■
■
“Variable Precision DSP Block Overview” on page 3–1
“Operational Modes Overview” on page 3–3
“Variable Precision DSP Block Resource Descriptions” on page 3–4
“Operational Mode Descriptions” on page 3–9
“Software Support” on page 3–23
High-performance, power-optimized, and fully registered multiplication
operations
Natively supported 9-bit, 18-bit, and 27-bit word lengths
Efficiently supported 18 x 25 complex multiplications for FFTs
Efficiently supported floating-point arithmetic formats
Built-in addition, subtraction, and 64-bit accumulation units to combine
multiplication results efficiently
Cascading 18-bit and 27-bit input bus to form tap-delay line for filtering
applications
®
V devices are optimized to support higher-bit precision in
3. Variable Precision DSP Blocks in
Stratix V Devices
Subscribe