DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 208
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
- Current page: 208 of 530
- Download datasheet (16Mb)
5–32
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Differential LVPECL
In Stratix V devices, the LVPECL I/O standard is supported on input clock pins on all
the I/O banks. LVPECL output operation is not supported in Stratix V devices. LVDS
input buffers are used to support LVPECL input operation. AC coupling is required
when the LVPECL common-mode voltage of the output buffer is not matched to the
LVPECL input common-mode voltage.
termination scheme. The 50-
device.
Figure 5–18. LVPECL AC-Coupled Termination
Note to
(1) The LVPECL AC/DC-coupled termination is applicable only when an Altera FPGA transmitter is used.
DC-coupled LVPECL is supported if the LVPECL output common mode voltage is
within the Stratix V LVPECL input buffer specification (refer to
Figure 5–19. LVPECL DC-Coupled Termination
Note to
(1) The LVPECL AC/DC-coupled termination is applicable only when an Altera FPGA transmitter is used.
RSDS
Stratix V devices support the true RSDS output standard with data rates up to
360 Mbps using true LVDS output buffer types on all I/O banks. Emulated RSDS
output buffers use two single-ended output buffers with external three-resistor
networks and can be tri-stated. They are available in all I/O banks (refer to
Figure
Figure
Figure
5–20).
Output Buffer
LVPECL
5–18:
5–19:
Output Buffer
LVPECL
0.1 μF
0.1 μF
Z
Z
0
resistors used at the receiver end are external to the
0
= 50 Ω
= 50 Ω
Z
Z
0
0
= 50 Ω
= 50 Ω
Figure 5–18
(Note 1)
(Note 1)
V
ICM
100 Ω
shows the AC-coupled
50 Ω
50 Ω
Chapter 5: I/O Features in Stratix V Devices
Termination Schemes for I/O Standards
Stratix V LVPECL
Input Buffer
May 2011 Altera Corporation
Figure
Stratix V LVPECL
Input Buffer
5–19).
Related parts for DK-DEV-5SGXEA7/ES
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: