DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 441

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Transceiver Clocking in Stratix V Devices
FPGA Fabric-Transceiver Interface Clocking
May 2011 Altera Corporation
Quartus II-Selected Transmitter Datapath Interface Clock
The Quartus II software automatically picks the appropriate clock from the FPGA
fabric to clock the transmitter datapath interface.
datapath interface of two non-bonded channels clocked by their respective
transmitter PCS clocks that are forwarded to the FPGA fabric.
Figure 2–18. Transmitter Datapath Interface Clocking for Non-Bonded Channels
Data and Control Logic
Channel 0 Transmitter
Data and Control Logic
Channel 1 Transmitter
FPGA Fabric
tx_coreclkin[1]
tx_coreclkin[0]
Transmitter Data
Transmitter Data
tx_clkout[1]
tx_clkout[0]
Figure 2–18
Stratix V Device Handbook Volume 3: Transceivers
Compensation
Compensation
Phase
Phase
FIFO
FIFO
TX
TX
shows the transmitter
Parallel Clock
Parallel Clock
Transmitter Data
Transmitter Data
Channel 1
Channel 0
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