DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 171

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Clock Networks and PLLs in Stratix V Devices
Stratix V PLLs
May 2011 Altera Corporation
Figure 4–27
clocks in external feedback mode.
Figure 4–27. Phase Relationship Between the PLL Clocks in External Feedback Mode
Note to
(1) The PLL clock outputs can lead or lag the fbin clock input.
Figure
4–27:
shows an example waveform of the phase relationship between the PLL
fbin Clock Input Pin
Clock Outputs (1)
Dedicated PLL
PLL Reference
Clock Port (1)
PLL Clock at
the Register
Clock at the
Input Pin
Phase Aligned
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
4–31