DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 340

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

10–2
Configuration Error Detection
User Mode Error Detection and Correction
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
In configuration mode, a frame-based 16-bit configuration CRC is stored in the
configuration data and contains the CRC value for each data frame.
During configuration, the Stratix V device calculates the 16-bit configuration CRC
value based on the frame of data that is received and compares it against the
pre-calculated 16-bit configuration CRC value in the data stream. If the 16-bit
configuration CRC values do not match, nSTATUS is set low. Configuration continues
until either the device detects an error or configuration is complete.
Stratix V devices offer on-chip circuitry for automated single event upset (SEU)
detection. Some applications require the device to operate error-free in high-neutron
flux environments require periodic checks to ensure continued data integrity. The
error detection CRC feature ensures data reliability and is one of the best options for
mitigating SEU.
You can implement the error detection CRC feature with existing circuitry in Stratix V
devices, eliminating the need for external logic. Stratix V devices have built-in error
detection circuitry to detect data corruption by soft errors in the configuration
random access memory (CRAM) cells. This feature allows all CRAM contents to be
read and verified to match a configuration-computed 32-bit error detection CRC
value. Soft errors are changes in a CRAM’s bit state due to an ionizing particle.
To enable the error detection process when the device transitions into user mode, turn
on the Enable Error Detection CRC_ERROR pin option on the Error Detection CRC
page of the Device and Pin Options dialog box in the Quartus II software.
The error detection capability continuously calculates the 32-bit error detection CRC
value of the configured CRAM bits and compares it with the configuration-computed
32-bit error detection CRC value. The 32-bit error detection CRC value is computed
during the configuration stage. The error detection circuitry generates 32 CRC check
bits per frame and then stores them in the CRAM. If the 32-bit error detection CRC
values match, there is no error in the current configuration CRAM bits. The process of
error detection continues until the device is reset by setting nCONFIG low.
A single 32-bit error detection CRC calculation is done on a per frame basis. After the
error detection circuitry has finished the CRC calculation for a frame, the resulting
32-bit signature is 000000000. If the error detection circuitry detects no CRAM bit
errors in a frame, the output signal CRC_ERROR is set to low. If the circuitry detects a
CRAM bit error in a frame in the device, the resulting signature is non-zero and the
error detection circuitry starts searching for the error bit location.
The error detection circuitry in Stratix V devices calculates CRC check bits for each
frame and pulls the CRC_ERROR pin high when it detects bit errors in the chip. Within a
frame, it can detect all single-bit, double-bit, triple-bit, quadruple-bit, and
quintuple-bit errors. The probability of more than five CRAM bits being flipped by a
SEU is very low. In general, the probability of detection for all error patterns is
99.9999%.
The error detection circuitry reports the bit location and determines the type of error
for single-bit errors or double-adjacent errors. The probability of other error patterns
is very low and the reporting of bit location is not guaranteed.
Chapter 10: SEU Mitigation in Stratix V Devices
May 2011 Altera Corporation
Configuration Error Detection