DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 329

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Remote System Upgrades
Table 9–16. Remote System Upgrade Registers
May 2011 Altera Corporation
Shift register
Control register
Update register
Status register
Register
This register is accessible by the logic array and allows the update, status, and control registers to be
written and sampled by user logic.
This register contains the current page address, user watchdog timer settings, and one bit specifying
whether the current configuration is a factory configuration or an application configuration. During a
read operation in an application configuration, this register is read into the shift register. When a
reconfiguration cycle is initiated, the contents of the update register are written into the control
register.
This register contains data similar to that in the control register. However, it can only be updated by the
factory configuration by shifting data into the shift register and issuing an update operation. When a
reconfiguration cycle is triggered by the factory configuration, the control register is updated with the
contents of the update register. During a capture in a factory configuration, this register is read into the
shift register.
This register is written to by the remote system upgrade circuitry on every reconfiguration to record
the cause of the reconfiguration. This information is used by the factory configuration to determine the
appropriate action following a reconfiguration. During a capture cycle, this register is read into the
shift register.
Remote System Upgrade Registers
The remote system upgrade block contains a series of registers that store the page
addresses, watchdog timer settings, and status information.
registers.
The remote system upgrade control and status registers are clocked by the 10-MHz
internal oscillator (the same oscillator that controls the user watchdog timer).
However, the remote system upgrade shift and update registers are clocked by the
user clock input (RU_CLK).
Control Register
The control register stores the application configuration page address and user
watchdog timer settings. The control register functionality depends on the remote
system upgrade mode selection. A factory configuration in remote update mode has
write access to this register.
Figure 9–30
register bits. In the figure, the numbers show the bit position of a setting in a register.
For example, bit number 25 is the enable bit for the watchdog timer.
Figure 9–30. Remote System Upgrade Control Register
37 36 35 34 33 32 31 30 29 28 27 26
shows the control register bit positions.
Wd_timer[11..0]
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Description
Wd_en
25
Table 9–17
24 23 22 .. 3
PGM[23..0]
Table 9–16
lists the control
2
1
lists these
AnF
0
9–49